oversampling為何有效？

上回談到oversampling，PS audio網站上談PerfectWav DAC http://www.psaudio.com/ps/products/description/perfectwave-dac?cat=audio
有這一段，其中的SRC便是sampling rate conversion

The PWD has one of the most sophisticate SRC's made providing 6 choices of sample rate improvement through the front panel touch screen. We included this sophisticated SRC for two reasons: it is expected and in some cases, beneficial. We also included a way to defeat the SRC.

This may all sound very strange as we have become used to the idea that "more is better". If 44.1 kHz is good, then surely 88.2 kHz is better and 192 kHz is the best. In some cases this is true but if you have a chance to audition the PWD and spend some time with this marvel you may discover that the ability to bypass the SRC is perhaps better in many cases.
SRC's manipulate data to do their work. DAC designers of nearly every company, including PS Audio, use them to lower incoming jitter and add features to the front panel. But years of research and a lot of engineering have demonstrated to us that while effective, use of the SRC can be a mixed bag.

We labeled the SRC bypass as "Native Mode" because it allows you to bypass completely the SRC's data manipulation and listen to the raw data as it is sent natively from the source. In most cases, Native Mode sounds far superior to any of the SRC choices, including 24 bit 192 kHz.
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The SRC is a valuable feature when the source you are using is of rather low digital quality such as that from an Apple TV, low cost CD player, Squeezebox, Sonos or third party network enabled system.

重點在這句 use them to lower incoming jitter

或許這個隨便的推論可以解釋這點...
設理想clock序列的時間值為 i[n]，則i[n] = 1/(sampling rate) * n
jitter j[n]為對i[n]值之時間變異（漂移量），j[n]可為正值也可為負值
則所得之實際clock時間值為c[n] = i[n] + j[n]
假設oversampling後所得之clock時間值c'[n]為取原始clock時間值interpolation而來，
則 c'[2n+1] = (c[n] + c[n+1])/2 = (i[n] + i[n+1])/2 + (j[n] + j[n+1])/2
其中(i[n] + i[n+1])/2 = i'[2n+1]正是理想之時間值
而(j[n] + j[n+1])/2則是jitter可表為j'[2n+1]
若j[n], j[n+1]一為正、一為負，則(j[n] + j[n+1]) <>
若二者皆為正或負，則abs(j[n] + j[n+1]) < max(abs(j[n], abs(j[n+1]))/2
也就是說，j'[2n+1] 絕對會是< max(abs(j[n], abs(j[n+1])/2
顯然jitter被平均化了，換句話說smooth化了...
或許因此，oversampling較佳！

由以上的推論，
若是jitter相當random，也就是j[n]與j[n+1]之間的差異較大，
則j'[2n+1]的值與j[n]、j[n+1]之間的差值較大，
則oversampling後的clock c'[2n+1]便較原本之clock c[n]更接近理想值

若原始之jitter j[n]極小呢？
則j[n]與j[n+1]相當接近，j'[2n+1]大約等於j[n]/2，
則oversampling減少jitter的效應便幾乎消失
這時其他的效應，例如熱雜訊，或許反倒佔了較大的比重，
而越是高頻，則越易受到這些背景的各種雜訊影響。

例如，假設oversampling電路部份的電源導致另一個jitter k[n]，
此k[n]對是否經過oversampling都有想同的影響，
因c'[n]每個period僅為c[n]之1/2，因此k[n]的影響便成為2倍！
反倒糟糕...