如何拿掉S/PDIF訊號的jitter？

在這篇裡

Single stage clock recovery means that there is one single PLL, that is used to recover the clock, attenuate the jitter, and retime the data. A single stage clock recovery circuit can be designed with high jitter attenuation performance at a reasonable price.Dual stage clock recovery uses two separate PLL circuits:The first PLL does only clock recovery. The recovered clock is input into the second PLL, that is used for jitter attenuation and data retiming.Dual stage clock recovery has the advantage, that the second PLL receives a clock signal (instead of a biphase mark signal) that is already cleaned by the first PLL.With dual stage clock recovery, a higher jitter attenuation is attainable, and the residual jitter can be more decorrelated from the input data stream. However dual stage often means dual price.....Dual stage Clock recovery can also be combined with a data buffer memory.The first PLL writes to the buffer, and the second PLL reads from the buffer and tries to keep it always half filled.If we use a FIFO (first in first out) memory as a data buffer, we have more time to react to clock variations of the input signal and thus are able to attenuate lower jitter frequencies. The larger the buffer, the lower the jitter frequency that can be attenuated.